The invention relates to a single-port memory cell and a semiconductor memory having single-port memory cells.
Single-port memory cells is a term designating all memory cells which have only a single selection line and a single data line. Hereinafter, unless expressly specified otherwise, all single-port memory cells are designated as memory cells for short.
A dynamic single-port memory cell (dynamic random access memory; DRAM) contains a selection transistor and a capacitive element. The capacitive element is in this case typically designed as a storage capacitor. As an alternative, it would also be conceivable for the capacitive element to be realized as a conventional memory transistor whose gate terminal is connected to a supply potential.
The particular advantage of DRAM memory cells consists in their extremely space-saving realization on a semiconductor chip, as a result of which DRAM semiconductor memories can be fabricated extremely cost-effectively. On account of the small number of circuit elements of a DRAM memory cell and hence the small outlay on wiring, DRAM semiconductor memories advantageously have very short access times, as a result of which their performance can additionally be optimized. However, in DRAM memory cells, a respective terminal of the capacitive element is at a xe2x80x9cfloatingxe2x80x9d potential, i.e. at an undefined potential. DRAM memory cells therefore have to be recharged at regular intervals (refresh operation). During this refresh operation, it is not possible to read from or write to the DRAM memory cell, as a result of which undefined switching states can never be completely avoided.
U.S. Pat. No. 4,203,159 describes a single-port memory cell arrangement having single-port memory cells having a capacitive element and a selection transistor, which are arranged between a data line and a supply line. Each cell has a controllable switch via which the capacitive element can be recharged.
Furthermore, U.S. Pat. No. 4,292,677 discloses using a MOS arrangement as a capacitive element. This MOS arrangement comprises a metal plate which, in a manner isolated by an oxide layer, lies above a semiconducting region of a main area of a semiconductor substrate. Corresponding potentials on the metal plate and the semiconductor substrate are used to produce a depleted region in the semiconductor region below the metal plate. In this region it is possible to store charges for generating logic states.
A static single-port memory cell (static random access memory; SRAM) typically contains six transistors: in each case two selection transistors (transfer gates) and four memory transistors (inverters). Although such an SRAM memory cell has defined potential states in its output path, as a result of which the information stored in the memory cell is preserved, distinctly more transistor elements are required for an SRAM memory cell in comparison with the DRAM memory cell described above. Therefore, also on account of the very much greater outlay on wiring, such an SRAM memory cell has an areally more complicated design than a DRAM memory cell. In particular highly complex semiconductor memories, in which area optimization constitutes the most important boundary condition, are therefore preferably constructed from DRAM memory cells.
The present invention is therefore based on the object of providing a new design of a single-port memory cell.
According to the invention, this object is achieved by means of a single-port memory cell having the features of patent claim 1.
In the preferred configuration, the single-port memory cell according to the invention in each case has a CMOS memory transistor and a CMOS selection transistor, whose load paths are connected in series, and this series circuit is arranged between a data line and a charging device. This arrangement makes it possible to provide a single-port memory cell in which a capacitive element can be read from or written to by means of a data processing device and, at the same time, this capacitive element can be recharged by means of the charging device (refresh operation).
Consequently, the new memory cell at least in part combines the DRAM memory cell functionality mentioned in the introduction with that of an SRAM memory cell. From the user""s perspective, the memory cell according to the invention behaves like a simple SRAM memory cell since it has defined switching states at every point in time. Consequently, the memory cell can be addressed at any time by a data processing unit. Compared with a conventional SRAM memory cell, the memory cell according to the invention additionally has the advantage of a distinctly reduced chip area. Conventional SRAM memory cells have a total of six transistors, while the memory cell according to the invention only requires a maximum of two or three transistors. Consequently, a saving in area of more than 50% can be realized.
The memory cell according to the invention is particularly advantageous in particular because the capacitive element is designed as a CMOS transistor. In the case of such a CMOS transistor, the load path terminal nodes thereof, i.e. the source terminal and the drain terminal, can coincide with the respective series-connected selection transistor and switching transistor in a space-saving manner. An optimal area design can be provided by virtue of this saving of area-intensive terminal nodes.
Furthermore, on account of the short interconnect lengths, the memory cell according to the invention has an access time which is optimized compared with conventional SRAM memory cells. Such short access times or such a small area requirement on the semiconductor chip has been achievable hitherto only by conventional DRAM memory cells.